1. Field of the Invention
The invention relates to a load stage comprising:
a first, a second and a third terminal; PA1 a first transistor having a gate, which is coupled to the first terminal, a source, a drain and a main current path between the source and the drain, which main current path is included in a current path between the first terminal and the third terminal; PA1 a second transistor having a gate, which is coupled to the second terminal, a source, a drain and a main current path between the source and the drain, which main current path is included in a current path between the second terminal and the third terminal; PA1 a third transistor having a gate, which is coupled to the second terminal, a source, a drain and a main current path between the source and the drain, which main current path is included in a current path between the first terminal and the third terminal; PA1 a fourth transistor having a gate, which is coupled to the first terminal, a source, a drain and a main current path between the source and the drain, which main current path is included in a current path between the second terminal and the third terminal; PA1 and PA1 switching means for selectively connecting the main current path of the first transistor and the main current path of the third transistor between the first and the third terminal and for selectively connecting the main current path of the second transistor and the main current path of the fourth transistor between the second and the third terminal.
2. Description of the Related Art
The invention also relates to a clocked comparator comprising such a load stage.
Such a load stage is known from a paper by B. S. Song and M. F. Tompsett, "A 10b 15 Mhz Recycling Two-Step A/D Converter", published in the Digest of Technical Papers, 1990 IEEE International Solid-State Circuits Conference, pp. 158-159. The known load stage is used in a clocked comparator. In a first phase of a clock signal the comparator operates as a differential amplifier, the impedance of the load stage being positive. In a second phase of the clock signal the comparator operates as a latching circuit, the impedance of the load stage being negative. In the known load stage the first and the second transistor are connected as dimes and their sources can be connected to the third terminal by a switching transistor, said third terminal being connected to earth. The gates of the third and the fourth transistor are cross-coupled to the drains of the third and the fourth transistor and the sources are connected to the third terminal via a permanently conductive switching transistor. The set with the cross-coupled third and fourth transistors forms a permanent negative differential impedance between the first and the second terminal. The other set with the diode-connected first and second transistors forms a positive differential impedance between the first and the second terminal, which is arranged in parallel with the negative differential impedance in the first phase of the clock signal.
A disadvantage of this known method of changing over the differential impedance is that the common-mode voltage on the first and second terminals is also varied by turning on and turning off the first and the second transistor. This is because the common-mode current will be distributed over both transistor sets in the first phase of the clock signal and over only one transistor set in the second phase. The shift in common-mode voltage may give rise to an undesired differential voltage component if the first and second terminals have unequal capacitive loads and may thereby adversely affect the accuracy of the clocked comparator.